Altiumcustomize

Design Rule Verification Report

Date : 10. 6. 2014
Time : 11:35:14
Elapsed Time : 00:00:01
Filename : S:\FEDEVEL\LVDS Adapter Type 1\V1I1\LVDS Adapter Type 1_PCB_V1I1.PcbDoc
Warnings : 0
Rule Violations : 0

Summary

Warnings Count
Total 0

Rule Violations Count
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Clearance Constraint (Gap=0.2mm) (All),(All) 0
Width Constraint (Min=0.25mm) (Max=4mm) (Preferred=0.25mm) (All) 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) 0
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All) 0
Hole To Hole Clearance (Gap=0.1mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.1mm) (All),(All) 0
Silk To Solder Mask (Clearance=0.1mm) (IsPad),(All) 0
Silk to Silk (Clearance=0.1mm) (All),(All) 0
Net Antennae (Tolerance=0mm) (All) 0
Matched Net Lengths(Tolerance=0.127mm) (InDifferentialPairClass('DIFF100')) 0
Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Total 0